1. Field of the Invention
This invention relates generally to application specific integrated circuits (ASICs) and in particular to a fail-safe structure that is included within the ASIC manufacturing test circuitry to assure that the test circuitry does not degrade the performance of the ASIC.
2. Description of the Related Art
In an application specific integrated circuit (ASIC), there are two general problems encountered in the manufacturing testing process. The first problem is that the ASIC logic itself is defective and the second is that the circuitry used to get signals into the ASIC logic and out of the ASIC logic is defective. Consequently, test logic is built into an ASIC that is used only in the manufacturing process to verify the operability of the ASIC. After the manufacturing process is complete, the ASIC test circuitry is passive and is no longer required or used.
Typically, the ASIC built-in test logic includes a built-in self-test (BIST) capability as well as a boundary scan capability. ASIC 100 (FIG. 1) includes both the built-in self-test capability and the boundary scan capability. ASIC 100 includes test logic 120, which controls the built-in self-test and the boundary scan capability, and ASIC logic 110.
The boundary scan capability is provided by input boundary scan register cells (BSRCs) 103-1 to 103-4, output boundary scan register cells 104-1 to 104-4, and test logic 120. The built-in self-test capability is provided by pseudo-random number generator cells 105-1 to 105-4, pseudo-random number signature analyzer cells 106-1 to 106-4, and test logic 120. ASIC 100 has four input pins 101-1 to 101-4 and four output pins 102-1 to 102-4.
As illustrated in FIG. 1, the configuration of the input and output boundary scan register cells 103-1 to 103-4 and 104-1 to 104-4 and pseudo-random number generator and signature analyzer cells 105-1 to 105-4 and 106-1 to 106-4 for each input pin and output pin is the same. Thus, the following description for input pin 101-2 and output pin 102-2 is applicable for any of the other input pins and output pins, respectively, of ASIC 100.
Input pin 101-2 drives an input boundary scan register cell 103-2, which in turn provides an input signal to pseudo-random generator cell 105-2 that in turn drives an input line of ASIC logic 110. Similarly, a signal on an output line of ASIC logic 110 drives pseudo-random number signature analyzer cell 106-2. The output signal of cell 106-2 drives output boundary scan cell 104-2, which in turn drives output pin 102-2.
Test logic 120 drives control lines for the input and output boundary scan cells and the pseudo-random number generator and signature analyzer cells. Typically, the built-in self-test and the boundary scan capability form an on-chip monitor architecture that conforms to IEEE 1149.1 standard. This standard requires that ASIC 100 have four additional pins, which are test data in signal pin TDI, test data out signal pin TDO, test mode select signal pin TMS, and test clock pin TCK. Test reset pin TRST* is an optional pin, but when test reset pin TRST* is used, the standard defines its use. In addition, most ASICs include, as illustrated for ASIC 100, an asynchronous ASIC reset pin RST and an asynchronous three-state output pin TRIST for use in normal operation of ASIC logic. However, for manufacturing tests, test logic 120 also typically includes a means for generating signals on lines TRISTATE and RESET to ASIC logic 110.
The built-in self-test typically includes an internal scan capability in addition to the boundary scan capability. The internal scan capability receives input signals from pin TDI, passes the signals through test logic 120 to ASIC logic 110 and the resulting signals from ASIC logic 110 are passed through test logic 120 to pin TDO. Test logic 120 generates a signal on line SS to configure flip-flops in ASIC logic 110 for the internal scan and in addition provides a clock signal CLK for the scan.
A common problem in manufacturing testing of ASIC 100 is that ASIC 100 fails to operate. The ASIC failure could be due to a multiplicity of reasons. For example, ASIC logic 110 could be defective. Alternatively, either test logic 120 or one or more of the cells used in the built-in self-test and boundary scan capability could be defective, and therefore prevent operation of the ASIC 100.
Unfortunately, at the time of manufacturing testing, there is no ability to determine the basis for the failure and typically the solution is to start over in the fabrication of ASIC 100 within a redesign of ASIC 100.
Also, either the boundary scan capability or the built-in self-test capability may introduce problems in the operation of ASIC 100, after ASIC 100 is provided to the customer. Ideally, the manufacturing test circuitry in ASIC 100 is only used during the manufacturing check out period and after that time is passive and its presence is unknown to the user. However, if, for example, the signal on line SS goes active after the customer receives ASIC 100, ASIC 100 goes into the internal scan mode, and therefore is no longer functional. Similarly, failures in test logic 120 may generate active signals on line TRISTATE or RESET that render ASIC logic 110 inoperable.
Failures in test logic 120 may create erroneous conditions in the input boundary scan register cells, the output boundary scan register cells, the pseudo-random number generator cells or the pseudo-random number signature analyzer cells. Any one of these faults in test logic 120 renders ASIC 100 inoperable.
The faults that may render ASIC 100 inoperable are further demonstrated by examining typical cells in ASIC 100 that are used that are used only for manufacturing testing.
A typical structure for an input boundary scan register cell 203 and a typical structure for an output boundary scan register cell 304 are illustrated in FIGS. 2 and 3, respectively. Input boundary scan register cells 103-1 to 103-4 are identical and are represented by cell 203 (FIG. 2). Output boundary scan register cells 104-1 to 104-4 are also identical and are represented by cell 304 (FIG. 3). Moreover, the basic structure of cell 203 and cell 304 are the same. The only difference in cells 203 and 304 is the source of the input signal for the cell and the use of the output signal from the cell.
Each cell 203, 304 includes two two-to-one multiplexers 211, 214 and 311, 314 and two D-type flip-flops 212, 213 and 312, 313. Test logic 120 drives five control lines which are used by cells 203, 304. If the signal on control line MODE is active, the input signal to cell 203, 304 is not simply passed through the cell. Rather, multiplexer 214, 314 passes the signal generated by D-type flip-flops 212, 213 and 312, 313 to the cell output line. Therefore, if test logic 120 drives the signal on line MODE permanently active, ASIC 100 is rendered useless.
A typical structure for a pseudo-random number generator cell 405 and a typical structure for a pseudo-random number signature analyzer cell 506 are illustrated in FIGS. 4 and 5 respectively. Pseudo-random number generator cell 405 (FIG. 4) represents pseudo-random number generator cells 105-1 to 105-4 and pseudo-random number signature analyzer cell 506 (FIG. 5) represents pseudo-random number signature analyzer cells 106-1 to 106-4. Each cell 405, 506 includes an exclusive OR gate, 416, 516, a D-type flip-flop, 417, 517, and a two-to-one multiplexer 418, 518. Each cell 405, 506 receives three control signals from test logic 120. If signal TEST.sub.-- MODE is active, the pseudo-random number built-in self-test feature is enabled. Accordingly, if signal TEST.sub.-- MODE goes active due to a fault in test logic 120, ASIC 100 is defective.
One difference in cells 405 and 506 is the source of the input signal and the use of output signal of the cell. The other difference is the number of input lines to the exclusive OR gate.
FIG. 6 illustrates a typical cell 600 within ASIC logic 110 that is used for internal scan testing. If the signal on line SS goes active for whatever reason, the ASIC logic that utilizes the flip-flops in the internal scan cell 600 becomes useless.
Thus, while the boundary scan capability and the built-in self-test capability included in ASIC 100 improved the testability of ASIC 100, these features also provide additional failure modes for ASIC 100. If these failure modes require re-design of ASIC 100 during manufacture, significant costs and delays in time to market are incurred. If these failure modes occur while ASIC 100 is being used by a customer, the customer is severely inconvenienced by the costs associated with the down time of the piece of equipment as well as the costs of replacing the failed ASIC. These losses result from passive equipment, which is used only in manufacturing testing, subsequently failing in a way that destroys the functionality of ASIC 100.